diff --git a/src/cpu.rs b/src/cpu.rs
index a0143e2..dc957dc 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -96,7 +96,7 @@ impl Cpu {
                 use HaltState::*;
 
                 match state {
-                    ImeSet | NonePending => Cycle::new(4),
+                    ImeEnabled | NonePending => Cycle::new(4),
                     SomePending => todo!("Implement HALT bug"),
                 }
             }
@@ -470,7 +470,7 @@ impl From<u8> for Flags {
 
 #[derive(Debug, Clone, Copy)]
 pub enum HaltState {
-    ImeSet,
+    ImeEnabled,
     NonePending,
     SomePending,
 }
diff --git a/src/instruction.rs b/src/instruction.rs
index a20d901..2e7897c 100644
--- a/src/instruction.rs
+++ b/src/instruction.rs
@@ -612,7 +612,7 @@ impl Instruction {
                 let enabled = cpu.read_byte(0xFFFF);
 
                 let halt_state = if let ImeState::Enabled = cpu.ime() {
-                    ImeSet
+                    ImeEnabled
                 } else if req & enabled != 0 {
                     SomePending
                 } else {