diff --git a/src/cpu.rs b/src/cpu.rs index 681fe8b..9fad643 100644 --- a/src/cpu.rs +++ b/src/cpu.rs @@ -104,10 +104,10 @@ impl Cpu { Instruction::execute(self, instruction) } - /// Perform the [`Cpu::fetch()`] [`Cpu::decode(opcode)`] [`Cpu::execute(instr)`] + /// Perform the [`Cpu::fetch()`] [`Cpu::decode()`] [`Cpu::execute()`] /// routine. /// - /// Handle HALT state and interrupts. + /// Handle HALT and interrupts. pub fn step(&mut self) -> Cycle { // Log instructions // if self.reg.pc > 0xFF { diff --git a/src/instruction.rs b/src/instruction.rs index fdee872..c99e709 100644 --- a/src/instruction.rs +++ b/src/instruction.rs @@ -1531,7 +1531,8 @@ impl Instruction { /// Set program counter to Address. /// - /// This is explicitly meant to emulate the exact behaviour of JP, JR RET, RETI and CALL + /// This is explicitly meant to emulate the exact behaviour of [`Instruction::JP`], [`Instruction::JR`] + /// [`Instruction::RET`], [`Instruction::RETI`] /// (4 cycles) fn jump(cpu: &mut Cpu, addr: u16) { cpu.set_register_pair(RegisterPair::PC, addr);