diff --git a/src/bus.rs b/src/bus.rs
index 892f387..8d60b36 100644
--- a/src/bus.rs
+++ b/src/bus.rs
@@ -123,14 +123,14 @@ impl Bus {
 
                 match self.cart.as_ref() {
                     Some(cart) => cart.read_byte(addr),
-                    None => panic!("Tried to read from a non-existent cartridge"),
+                    None => 0xFF,
                 }
             }
             0x8000..=0x9FFF => self.ppu.read_byte(addr), // 8KB Video RAM
             0xA000..=0xBFFF => match self.cart.as_ref() {
                 // 8KB External RAM
                 Some(cart) => cart.read_byte(addr),
-                None => panic!("Tried to read from a non-existent cartridge"),
+                None => 0xFF,
             },
             0xC000..=0xCFFF => self.work_ram.read_byte(addr), // 4KB Work RAM Bank 0
             0xD000..=0xDFFF => self.var_ram.read_byte(addr),  // 4KB Work RAM Bank 1 -> N
@@ -176,7 +176,7 @@ impl BusIo for Bus {
 
                 match self.cart.as_ref() {
                     Some(cart) => cart.read_byte(addr),
-                    None => panic!("Tried to read from a non-existent cartridge"),
+                    None => 0xFF,
                 }
             }
             0x8000..=0x9FFF => {
@@ -189,7 +189,7 @@ impl BusIo for Bus {
             0xA000..=0xBFFF => match self.cart.as_ref() {
                 // 8KB External RAM
                 Some(cart) => cart.read_byte(addr),
-                None => panic!("Tried to read from a non-existent cartridge"),
+                None => 0xFF,
             },
             0xC000..=0xCFFF => self.work_ram.read_byte(addr), // 4KB Work RAM Bank 0
             0xD000..=0xDFFF => self.var_ram.read_byte(addr),  // 4KB Work RAM Bank 1 -> N
@@ -279,9 +279,8 @@ impl BusIo for Bus {
             0x0000..=0x7FFF => {
                 // 16KB ROM bank 00 (ends at 0x3FFF)
                 // and 16KB ROM Bank 01 -> NN (switchable via MB)
-                match self.cart.as_mut() {
-                    Some(cart) => cart.write_byte(addr, byte),
-                    None => panic!("Tried to write into non-existent cartridge"),
+                if let Some(cart) = self.cart.as_mut() {
+                    cart.write_byte(addr, byte);
                 }
             }
             0x8000..=0x9FFF => {
@@ -293,9 +292,8 @@ impl BusIo for Bus {
             }
             0xA000..=0xBFFF => {
                 // 8KB External RAM
-                match self.cart.as_mut() {
-                    Some(cart) => cart.write_byte(addr, byte),
-                    None => panic!("Tried to write into non-existent cartridge"),
+                if let Some(cart) = self.cart.as_mut() {
+                    cart.write_byte(addr, byte);
                 }
             }
             0xC000..=0xCFFF => self.work_ram.write_byte(addr, byte), // 4KB Work RAM Bank 0
diff --git a/src/emu.rs b/src/emu.rs
index b04b96b..2f8c27c 100644
--- a/src/emu.rs
+++ b/src/emu.rs
@@ -120,7 +120,7 @@ impl Emulator {
                 save_path.set_extension("sav");
 
                 if let Ok(mut file) = File::open(&save_path) {
-                    tracing::info!("Loading {:?}", save_path);
+                    tracing::info!("Load {:?}", save_path);
 
                     let mut memory = Vec::new();
                     file.read_to_end(&mut memory)?;
diff --git a/src/ppu.rs b/src/ppu.rs
index 52c23ce..ccb253d 100644
--- a/src/ppu.rs
+++ b/src/ppu.rs
@@ -369,7 +369,7 @@ impl Ppu {
                     }
                 }
                 ToFifoA => {
-                    if let Ok(_) = self.fetch.send_to_fifo(&mut self.fifo) {
+                    if self.fetch.send_to_fifo(&mut self.fifo).is_ok() {
                         self.fetch.x_pos += 1;
                         self.fetch.back.state = ToFifoB;
                     }